Non-volatile memory devices (such as flash E2PROMs) are commonly used to store information, which must be preserved even in the absence of an electric power source that supplies the memory device. Typically, the memory device includes a matrix of memory cells, for example, arranged in rows and columns. Each memory cell consists of a MOS transistor having a floating gate insulated from both a channel and a control gate by oxide layers. The transistor is programmed by injecting an electric charge into its floating gate, exploiting a physical phenomenon known as Channel Hot Electron (CHE) injection. The electric charge in the floating gate modifies the threshold voltage of the transistor, in such a way as to define different logic values. The transistors are erased in blocks by removing the electric charge from their floating gates.
The memory device further includes a bit line for each column of the matrix, and a word line for each row of the matrix. A typical matrix architecture is the so-called NOR architecture, according to which all the memory cells of a same column are connected, in parallel to each other and by their drain terminals, to a same bit line, while all the memory cells of a same row are connected by their control gate terminals to a same word line.
Typical NOR flash memories are manufactured in such a way that a source region is generally realized by means of a single source diffusion for the memory cells belonging to a same word line. Said source diffusion is connected to a metallic line every, e.g., 16 memory cells along the word. All the source diffusions are short-circuited to each other.
According to an alternative known manufacturing typology, each source diffusion (for the memory cells belonging to a same word line) is connected to an independent metallic line, which can be accessed individually. In this way, each source line is electrically independent from the others, so as to increase the granularity of the erase operations.
Normally, for programming a selected memory cell, voltage pulses are simultaneously applied to the control gate terminal and to the drain terminal of the corresponding transistor. This operation can be performed in the matrix by selectively applying the pulses to the word line at which the control gate of the selected transistor is connected, and to the bit line at which the drain of the selected transistor is connected. Consequently, a lateral electric field occurs between the drain and the source of the selected transistor; such lateral electric field is capable to energize (or “heat”) the electrons that are present in its channel. Moreover, also a transversal electric field occurs between the channel and the control gate of the selected transistor. The transversal electric field promotes the injection of the electrons that are sufficiently energized (CHE) through the oxide layer separating the channel from the floating gate. The occurrence of such electron injection starts when the magnitude of the transversal electric field is sufficiently high (depending on the thickness of the oxide layer). During this operation the source terminals of all the transistors are kept to a reference voltage (or ground). In some applications, wherein insulation by triple-well can be exploited for the manufacturing of the memory device, the substrate in which the transistors are integrated can be biased with a negative voltage in such a way to increase the injection efficiency (Channel Initiated Secondary Electron Injection (CHISEL) effect).
Therefore, during a program operation, only the bit lines and the word line at which the selected memory cells belong to are biased with positive voltages, while all the other word lines are normally kept grounded and all the other bit lines are normally kept floating.
This biasing scheme is however not optimal, because it implies the occurrence of parasitic phenomena that may dangerously damage the oxide layer separating the channel from the floating gate and, in case the entity of such parasitic phenomena are strong enough, may affect the state of other memory cells of the matrix. More particularly, the unselected memory cells sharing the same bit line with a selected memory cell under programming are subjected to a positive drain voltage and to a null control gate voltage (with a negative substrate voltage, if it is possible, and a null source voltage). Each one of the corresponding transistors is in an electrical condition favorable for the occurrence of a physical phenomenon known as Band to Band Tunneling (BBT). According to such phenomenon, electron-hole pairs are generated at the reverse biased drain/substrate junction by electron tunneling, thereby provoking a parasitic drain stress capable to degrade the content of the memory cell itself. As it is known from experimental analysis results, the number of electron-hole pairs that are generated in this way increases if the voltage difference between the control gate terminal and the channel has a negative value, as in the case of a programmed cell (wherein a quantity of negative electrical charge is trapped within its floating gate, with a null control gate voltage). Furthermore, in this case the holes generated by the BBT phenomenon are injected into the oxide layer, which is thus subjected to an excessive stress that may result in a critical damage thereof; in turn, this provokes the generation of an anomalous Stress Induced Leakage Current (SILC), i.e., a current through the oxide layer when an electrical field of low intensity is induced across the oxide layer itself. The presence of such a current may cause an increasing or a decreasing of the electrical charge stored in the floating gate, which is even capable to change the state of the memory cell in an incorrect way.